Bitline structure and method for production thereof

ABSTRACT

The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer ( 6 ) and being connected to doping regions ( 10 ) with which contact is to be made via a covering connecting layer ( 12 ) and a self-aligning terminal layer ( 13 ) in an upper partial region of the trench.

REFERENCE TO RELATED APPLICATIONS

This application is related to and claims the benefit of priority under35 U.S.C. §§ 120, 271 and 365 to Patent Cooperation Treaty patentapplication no. PCT/DE2003/002676, filed on Aug. 8, 2003, which waspublished at WO 2004/023553, in German.

This application is further related to and claims benefit of priorityunder 35 U.S.C. § 119 to the filing date of Sep. 2, 2002 of Germanpatent application no. 10240436.4 DE, filed on Sep. 2, 2002.

FIELD OF THE INVENTION

The present invention relates to a bit line structure and to a method offabrication thereof, and in particular to a sub-100 nm bit linestructure and an associated fabrication method that can be used in anonvolatile Selective NOR (“SNOR”) memory circuit for in each caseselectively driving source and drain lines.

BACKGROUND

When realizing memory circuits, a basic distinction is drawn on thebasis of the storage architecture; the most common representatives arereferred to as the NAND and NOR architectures. In both architectures,one-transistor memory cells are arranged in matrix form and are drivenvia signal connections referred to as word and bit lines.

Whereas in NAND architectures a multiplicity of switching elements orstorage elements are connected in series with one another and are drivenvia a common selection gate or a selection transistor, the respectiveswitching elements in NOR architectures are organized in parallel or inmatrix form, as a result of which each switching element can be selectedindividually.

FIG. 1 shows a simplified illustration of a so-called SNOR architecture(selective NOR), in which, in contrast to the NOR architecture with“common source” structure, the individual switching elements SE1, SE2, .. . are driven selectively via a respective source line SL1, SL2, . . .and via a respective drain line DL1, DL2,. . . . This selective drivingis carried out for example by means of respective bit line controllersBLC which, as it were, realize the common bit lines BL1, BL2,. . . .Further shrinks or more extensive integration of semiconductor circuitarrangements can be carried out in this way, since the SNOR architecturedoes not rely on a predetermined minimum cell transistor length orchannel length.

FIG. 2 shows a simplified illustration of a conventional layout of theSNOR architecture in accordance with FIG. 1. In accordance with FIG. 2,the switching elements or memory elements SE1, SE2, . . . are formed inactive areas AA of a semiconductor substrate which have a substantiallystraight strip-type structure. On the multiplicity of strip-type activeareas AA arranged in columns there overlie, in rows, layer stacks orword line stacks WL1, WL2, . . . likewise formed in strip form. Eachcrossover point or overlap region between such a strip-type active areaAA and a word line stack WL1 to WL3 formed in strip form thus representsa multiplicity of switching elements or memory elements SE.

Contacts are necessary for making contact with respective drain regionsD and source regions S, which contacts are usually formed in the activeareas AA, but may often also extend into an adjoining isolation regionSTI (Shallow Trench Isolation). In a further layer lying above that,which preferably represents a first metallization layer, there are thensituated the source lines SL1, SL2, . . . and also the drain lines DL1,DL2, . . . for the respective bit lines BL. In this case, the drainlines are connected to the associated drain regions D of the active areaAA via corresponding contacts K, the source lines being connected to theassociated source regions S via corresponding contacts in the same way.

What is disadvantageous, however, in the case of such a conventional bitline structure is that a more than twice as intensive metallization ispresent on account of the additional source lines in comparison with acommon source architecture, which represents a limiting factor for moreextensive integration or further shrinks.

Therefore, to improve an integration density, it is proposed, inaccordance with document DE 100 62 245 A1, to form the source lines anddrain lines as spacers at an insulating web and to allow contact to bemade with the associated source regions and drain regions via anadditional insulation layer with suitable openings. Furthermore,however, the space required on account of the source lines and drainlines formed at the substrate surface and lying parallel is relativelylarge and prevents more intensive integration.

Furthermore, document U.S. Pat. No. 6,008,522 has disclosed a buried bitline which is formed in an insulation trench and in each case makessymmetrical contact with source regions and drain regions via a terminallayer.

Accordingly, a bit line structure and an associated fabrication methodis needed, which, in particular with SNOR architectures, allows furtherintegration to be realized with a reduced need for space.

SUMMARY

The present invention is defined by the following claims, and nothing inthis section should be taken as a limitation on those claims. By way ofintroduction, the preferred embodiments described below relate to a bitline structure for realizing SNOR architectures with a significantlyreduced need for space is obtained in particular by the use of a surfacebit line, which is formed above a substrate surface for connection of amultiplicity of first doping regions, and a buried bit line, which forconnection of a multiplicity of second doping regions is formed inside asubstrate, in such a manner that a trench in the substrate, a trenchinsulation layer at a trench surface of the trench, the buried bit linein a lower region of the trench, a covering insulation layer in a firstupper partial region of the trench, a multiplicity of coveringconnecting layers in a second upper partial region of the trench, and amultiplicity of self-aligning terminal layers in the region of thesubstrate surface are formed, the multiplicity of covering connectinglayers being electrically connected via the terminal layers to themultiplicity of second doping regions.

The substrate used is preferably a silicon semiconductor wafer, thecovering connecting layer used is preferably highly doped polysiliconand the self-aligning terminal layer is preferably a silicide, with theresult that the buried bit line with the associated doping regions canbe connected in a particularly simple way and with minimal featuresizes.

Particularly in the case of direct contact between the multiplicity ofconnecting layers and the substrate, improved substrate contact-makingor well-contact making, if wells are formed therein, is obtained, withthe result that, for example, more homogenous tunneling, improvedendurance with regard to the number of write/erase cycles and areduction in parasitic diodes can be achieved. Furthermore, inparticular in the case of a multiple well structure in the substrate, itis thereby possible to eliminate complex-surface well contacts, with theresult that the demand for space is further reduced.

It is preferable for drain regions to be formed as first doping regionsand source regions to be formed as second doping regions in anonvolatile SNOR semiconductor memory circuit, in which case associatedword line stacks have a first insulation layer, a charge-storing layer,a second insulation layer and a control layer. In this way, it ispossible to realize particularly area-optimized nonvolatilesemiconductor memories, such as for example flash EPROMs, E2PROMs and 5the like.

The preferred embodiments further relate to a method for fabricating abit line structure. In one embodiment, the method comprises a buried bitline with a covering insulation layer above it are formed in particularin a trench with a trench insulation layer, with both partial regions ofthe covering insulation layer being removed and a multiplicity ofcovering connection layers being formed therein using just one maskafter the doping regions have been formed, which covering connectinglayers then electrically connect the buried bit line to the seconddoping regions via a multiplicity of self-aligning closure layers. Inthis way, the area-optimized bit line structure can be formed verysimply and in a substantially self-aligning fashion.

The covering insulation layer preferably comprises a second coveringpartial layer which has been formed by means of a TEOS depositionprocess and is removed again in part or on a half side and is formeddirectly connected to the substrate by the covering connecting layer. Inthis way, using suitably doped semiconductor materials, it is possibleboth to insulate and make contact with the substrate of the buried bitline.

Alternatively, the covering insulation layer may also have a coveringsacrificial layer which is formed by means of a spacer process and isremoved partially or on a half side by means of a selective etchingprocess, with the result that greatly improved shielding properties inthe form of active shielding by the buried bit line are obtained in thetrench combined with a further reduced demand for space.

Further aspects and advantages of the invention are discussed below inconjunction with the preferred embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified equivalent circuit diagram of an SNORarchitecture.

FIG. 2 shows a simplified plan view of a layout in accordance with FIG.1 with a conventional bit line structure.

FIG. 3 shows a simplified plan view of a layout of a semiconductorcircuit with a bit line structure according to one embodiment.

FIG. 4 shows a simplified sectional view of the semiconductor circuitarrangement shown in FIG. 3 for the purpose of illustrating a bit linestructure in accordance with a first exemplary embodiment.

FIGS. 5A–5I show simplified sectional views illustrating importantmethod steps involved in the fabrication of a bit line structure inaccordance with the first exemplary embodiment.

FIGS. 6A–6F2 show simplified sectional views illustrating importantmethod steps involved in the fabrication of a bit line structure inaccordance with a second or third exemplary embodiment.

FIG. 7 shows a simplified sectional view illustrating a bit linestructure in accordance with a fourth exemplary embodiment.

DETAILED DESCRIPTION OF THE DRAWINGS AND PRESENTLY PREFERRED EMBODIMENTS

FIG. 3 shows a simplified plan view illustrating a bit line structureaccording to one embodiment as can be used, for example, in an SNORsemiconductor memory circuit. Identical reference symbols in this figuredenote identical or corresponding elements or layers to those shown inFIGS. 1 and 2. In accordance with FIG. 3, a multiplicity of active areasAA in strip form are formed in columns in a substrate which, by way ofexample, includes a semiconductor substrate and preferably silicon, bymeans of a multiplicity of trench isolations STI in strip form. As inthe prior art shown in FIG. 2, word line stacks WLx, where x=1 to n, areformed in lines perpendicular to these active areas AA in strip form atthe surface of the substrate. These word line stacks, are formed inorder to produce, for example, nonvolatile memory elements, having afirst insulation layer, such as for example a gate oxide layer ortunneling layer, a charge-storing layer, such as for example a floatinggate, a second insulation layer, such as for example an intermediatedielectric, and a control layer as the actual driving word line. Forinsulation purposes, side wall insulation layers or spacers SP areformed at the side walls of the word line stacks WLx. Accordingly, aswitching element or a nonvolatile memory element SE, which in order torealize a field-effect transistor structure has drain regions D andsource regions S as first and second doping regions at the sides of theword line stacks, is formed at each crossover point or overlap pointbetween the active areas AA and the word line stacks WLx.

However, to realize the area-optimized semiconductor circuit accordingto the disclosed embodiments, the bit line structure comprising a sourceline and drain line pair SLx and DLx where x=1 to m is formed not onlyat the surface of the substrate but also on the one hand as a buried bitline SLx in the trench isolation STI within the substrate and on theother hand as a surface bit line DLx at or above the substrate surface.More specifically, the buried bit line SLx is embedded in the lowerlayers of the trench isolation STI and is connected to the sourceregions S with which contact is to be made via locally formedself-aligning terminal layers 13. On the other hand, the surface bitline DLx, which is formed, for example, in a first metallization level,is connected to associated drain regions D of the switching elements SEvia contacts DC. This results in a bit line structure which is optimizedwith regard to the space required and in which in particular the pitchdimensions (feature size+feature spacing) can be significantly reduced.

In accordance with FIG. 3, the surface bit line DLx is formed in stripform above the active areas AA. On account of this rectilinear stripdesign, they can be defined lithographically in a relatively simple way.This will become particularly important in future. However, it may alsotake any other form in the same way.

FIG. 4 shows a simplified sectional view corresponding to Section A—Ashown in FIG. 3; identical reference symbols once again denote identicalelements or layers and their description will not be repeated below.

In accordance with FIG. 4, a semiconductor substrate a has a multilayerstructure or a multiple well structure, in which a first, for examplep-type well 3 and a second, for example n-type well 2 are formed in anactual semiconductor substrate 1 or a deep p-type well 1. A multiplewell structure of this type is advantageous in particular with regard toits shielding action and its insulation properties, since sufficientinsulation layers can be formed even in deep regions of the substrate,for example by means of space charge regions, and furthermore complexstructures can be realized.

Then, deep trenches, which at their trench walls have a trenchinsulation layer 6, have been formed in the semiconductor substrate orin the associated layers or wells 1, 2, 3. Then, the actual buried bitline SLx has been formed in a lower region of the trenches with theirtrench insulation layer 6 by means of an electrically conductive fillinglayer 7; a covering insulation layer having preferably one secondcovering partial layer 9 has been formed in an upper partial region ofthe trench or at a half side, this covering insulation layer preferablybeing formed by means of a STI (Shallow Trench Isolation) method. Inthis way, in accordance with FIG. 4, excellent insulation properties, inparticular in an upper region of the trench, are formed toward theleft-hand half side.

In the further upper partial region of the trench or at the right-handhalf side, the insulation layer 9 and the trench insulation layer 6 atassociated second doping regions 10 or source regions S have beencompletely removed and replaced by a multiplicity of terminal connectinglayers 12, which in turn are electrically conductive and make contactwith the buried bit line or filling layer 7. The second doping regions10 have been formed at the substrate surface between the insulationtrenches and preferably directly adjoin the trenches. Then, to connectthese second doping regions 10 to the buried. Bit line SLx,self-aligning terminal layers 13 have been formed between a mask layer11 in the region of the substrate surface and, in accordance with FIG.4, directly at the surface of the substrate. These self-aligningterminal layers 13, in the case of silicon semiconductor material,consist of silicide or salicides (self-aligned silicides).

To insulate the substrate, the second doping regions 10 and the terminallayers 13 from the layers above, an intermediate insulation layer 14 hasalso been formed, at the surface of which, finally, the structuredsurface bit lines DLx have been formed in strip form as structuredelectrically conductive layers 15.

This for the first time results in an area-optimized bit line structureeven for SNOR architectures which in particular has low demands withregard to the pitch (feature size+feature spacing) in metallizationlevels.

In accordance with FIG. 4, a semiconductor material (e.g. Si) of theopposite conduction type p+ to the second doping region 10 is used asburied bit line or electrical filling layer 7 and as covering connectinglayer 12. More specifically, by way of example, a p+-doped semiconductormaterial is used for the filling layer 7 and the covering connectinglayer 12, whereas the source region S is n+-doped and is located in thep-doped well 3. With an arrangement of this nature, in which inparticular the multiplicity of connecting layers 12, on account of theabsence of the trench insulation layer 6 in the upper partial region ofthe trench, are in direct contact with the substrate or the p-type well3, not only can contact be made with the source region S by means of theburied bit line, but so too can the p-type well 3, with the result that,in particular in the case of nonvolatile memory elements, such as forexample flash EPROM elements, a more homogenous tunneling behavior andan increased number of write/erase cycles (endurance) can be achieved.Furthermore, parasitic diodes or leakage currents can be significantlyreduced as a result. A further benefit of making direct contact with thesubstrate or a well of the substrate via the connecting layer 12 in thisway is the fact that there is no need for surface contacts, which wouldusually be required in order to realize a uniform potential in a well ofthis nature. Accordingly, in this way demands imposed on the layout canbe significantly relaxed.

FIGS. 5A–5I show simplified sectional views illustrating importantmethod steps involved in the fabrication of a bit line structure asshown in FIG. 4; identical reference symbols once again denote identicalor corresponding elements or layers, and these elements or layers willnot be described once again in the text which follows.

Accordingly, as shown in FIG. 5A, a multiplicity of wells are formed ina substrate, for example by means of ion implantation, forming, forexample, a deep p-type well 1, a shallow first well 3 and a secondn-type well 2. Of course, the deep well 1 may also simply be thesubstrate itself or alternatively it is possible for an even greaternumber of wells to be formed in the substrate. Then, a first auxiliaryinsulation layer 4 is formed at the surface of the semiconductormaterial, for example by deposition or growth of an oxide layer. This isfollowed by forming and patterning a hard mask layer 5, with siliconnitride preferably being formed at the surface of the first auxiliaryinsulation layer 4. The hard mask layer 5 is patterned usingconventional photolithographic methods and is substantially used todefine the trenches which are to be formed.

Then, in accordance with FIG. 5B, a deep trench T is formed in thesubstrate by means of the patterned hard mask 5; in accordance with theexemplary embodiment described, this trench extends down into the secondwell 2. In this context, it is preferable to use an anisotropic etchingprocess, such as for example reactive ion etching (RIE). This etchingstep is concluded, for example, by a cleaning step in which polymers orpolymer residues are removed.

Then, in accordance with FIG. 5C, a trench insulation layer 6 is formedover the entire trench surface of the trench T, a thermal oxidationpreferably being carried out in order to form what is known as a lineroxide. In principle, however, it is also possible to use otherinsulation layers instead of the silicon dioxide as trench insulationlayers 6; in particular, it is also possible to realize insulatingmultiple layers.

Then, to produce the buried bit line, an electrically conductive fillinglayer 7 is formed in the trench T or at the surface of the trenchinsulation layer 6. In this case, it is preferable to deposit highlydoped polysilicon in the trench, the doping being selected as a functionof the first well 3 used and the intended contact which is to be made.However, in principle it is also possible for other electricallyconductive layers, such as for example metals, to be formed in thetrench as buried bit line SLx.

In accordance with FIG. 5D, in a subsequent step first of all theelectrically conductive filling layer 7 is recessed; by way of example,an STI process can be used to realize shallow trench isolations and toform shallow trenches ST. The individual method steps involved in aconventional STI process of this type will not be dealt with in moredetail, since they are generally known to the person skilled in the art.

In accordance with FIG. 5E, in this case, following a preferablyanisotropic etching step, it is also possible for the trench edges ofthe hard m ask layer 5 to be etched back, which is known as a “nitridepullback”. This to a certain extent relieves the stresses at the trenchedges for further processing and also results in improved electricalproperties of, for example, CMOS transistors which are likewise presentin the semiconductor circuit.

Then, it is also possible to form a first covering partial layer 8 asinsulation layer at the surface of the filling layer 7 which has beenetched back; in this case it is once again preferable to carry out athermal oxidation to form a further liner oxide. Finally, a secondcovering partial layer 9 is formed as a further insulation layer, theupper region of the trench preferably being completely filled withsilicon dioxide by means of a TEOS deposition process. After aplanarizing step, such as for example a CMP (Chemical MechanicalPolishing) process, in which the hard mask layer 5 is used as a stoplayer, the sectional view illustrated in FIG. 5E is obtained.

Then, in accordance with FIG. 5F, the hard mask layer 5 or the siliconnitride is completely removed and optionally so too is the firstauxiliary insulation layer 4. At this point in time, by way of example,a first insulation layer (not shown) or gate oxide layer or tunnelingoxide layer is formed at the respective regions of the active area AA atthe semiconductor substrate. However, a first insulation layer of thistype is not required in the region of the sectional illustration, andconsequently it is eliminated and only the first doping regions (notshown) and second doping regions (shown) 10 are then formed as sourceand drain regions at the surface of the semiconductor substrate. Thesedoping regions 10 are formed, for example, by means of conventionalimplantation methods; it is also possible to carry out LDD or terminalimplantations using respective spacers.

Then, in accordance with FIG. 5G, a mask layer 11 or cap layer 11 isformed and is patterned in such a manner that in each case only apartial region, e.g. a half side, of the trench is covered. To realizethis mask layer 11, by way of example silicon dioxide or silicon nitrideis deposited and patterned, although it is also possible to use othermaterials, such as for example new types of metal oxides (ZrO2,Al2O3, .. .)

Then, in accordance with FIG. 5H, the uncovered partial region of thecovering insulation layer, comprising the trench insulation layer 6 andthe first and second covering partial layers 8 and 9, is completelyremoved using the mask layer 11 and by carrying out a, for example,strongly selective anisotropic oxide etching process, until the fillinglayer 7 is uncovered. This may also lead to an overetch (not shown) orfurther removal of the trench insulation layer 6 (cf. FIG. 4).

Then, in accordance with FIG. 5I, the covering connecting layer 12 or,as seen over the entire trench, a multiplicity of covering connectinglayers is formed at the corresponding locations in the etched-backpartial regions of the trench; this preferably involves deposition of insitu-doped polysilicon.

After this formation of the covering connecting layer 12 which iselectrically conductively connected to the filling layer 7, the firstand second doping regions 10 in the substrate are additionally etchedback, which ensures that there are no parasitic short circuits betweenadjacent source regions as a result of residues of covering connectinglayer 12. Then, a multiplicity of self-aligning terminal layers 13 areformed at the surface of the covering connecting layer 12 and of thedoping regions 10, resulting in an electrical connection between dopingregions 10 and covering connecting layer 12 or the buried bit lines. Toproduce highly conductive terminal regions 13 of this type, by way ofexample, first silicidable material or a silicidable metal layer, suchas for example cobalt, nickel or platinum, is deposited over the entiresurface. Then, the surface layer of the semiconductor material, thecovering connecting layer 12 and the doping regions 10 are transformedusing the silicidable material to form the highly conductive terminalregions 13, without any silicide being formed at those surfaces whichare not in contact with semiconductor material (silicon), i.e. at themask layer 11, but rather at these surfaces the material which has beendeposited (metal) remaining in place, which means that, in turn, themetal layer which has been deposited—but not silicided—can be etchedback selectively by means of a preferably wet-chemical etching process.In this way, both the self-aligning formation of the covering connectinglayer 12 and of the terminal layers 13 can be carried out by means of asingle mask or mask layer 11; furthermore, if suitable doping materialsare selected, direct contact can be made with the first well 3.

In the further steps (not illustrated), by way of example, the masklayer 11 can be removed again and the intermediate insulation layer 14illustrated in FIG. 4 and the metallization layer 15 can be formed andpatterned in order to realize the surface bit lines DLx. Finally, amultiplicity of contacts (DC) for electrically connecting the surfacebit line (DLx) to the first doping regions (B) is formed.

FIGS. 6A to 6F2 show simplified sectional views illustrating importantmethod steps involved in the fabrication of a bit line structure inaccordance with a second or third exemplary embodiment; identicalreference symbols denote identical or corresponding layers to thoseshown in FIGS. 1 to 5, and consequently these layers will not bedescribed again in the text which follows.

Similarly, as described above, preparatory steps are carried Out for thepurpose of forming in particular the trench T, the trench insulationlayer 6 and the etched-back filling layer 7, in accordance with FIGS. 5Ato 5D, for which reason specific reference is made at this point to thecorresponding description.

In accordance with FIG. 6A, after a method step as shown, for example,in FIG. 5D, the upper trench region is then not completely filled withthe first and second covering partial layers 8 and 9, but rather firstof all a covering sacrificial layer 8A is formed at the surface of thetrench insulation layer 6 in the upper trench region, for example bymeans of a spacer method. The covering sacrificial layer 8A should inthis case have an etching selectivity which is different than the trenchinsulation layer 6 and an insulation filling layer 9 which issubsequently to be formed. A spacer method of this type (formation of aconformal layer+anisotropic etchback) will not be described below, sinceit is generally known to the person skilled in the art.

Then, in accordance with FIG. 6B, in a similar way to the method stepshown in FIG. 5E, a second covering partial layer 9 for completelyfilling the trench is formed by means of, for example, a TEOS depositionprocess, and then a planarization process (CMP) is carried out and thehard mask layer 5 is removed.

Then, in accordance with FIG. 6C, a mask layer 11 is formed andpatterned at the surface of the substrate in such a manner that at leasta partial region of the trench is covered by the mask layer 11, whichpreferably involves covering half of the trench or of the trenchinsulation located in the upper trench.

Then, in accordance with FIG. 6D, according to a second exemplaryembodiment a highly selective isotropic etching process can be carriedout for the purpose of removing the covering sacrificial layer 8A; byway of example, if a silicon nitride layer is used as coveringsacrificial layer 8A, phosphoric acid can be used as etchant. However, adrawback of this is that, by way of example, silicon layers cannot beused for the mask layer 11, but instead insulation layers, such as forexample Al2O3, ZrO2, HfO2, etc.(metal oxides) are suitable for use asmask layer 11.

This results in a contact hole leading to the filling layer 7, which iscompletely insulated with respect to the substrate or the first well 3by the trench insulation layer 6, with the result that improvedinsulation properties are obtained for certain applications and the cellsurface area is reduced, since in this case, on account of theself-alignment, there is no need to plan in any photographic technologyreserve for typical misalignments.

Accordingly, in this second exemplary embodiment shown in FIG. 6E1, thetrench insulation layer 6 is retained even in the upper uncovered orunmasked region, with the result that, during thinning or recessing ofthe doping regions 10 which is subsequently carried out, there is lessrisk of over-etching occurring.

Then, in accordance with FIG. 6F1, the covering connecting layer 12 isonce again formed, as in FIG. 51, the doping region 10 is (optionally)recessed and the highly conductive terminal layer 13 is formed in aself-aligning fashion. This results in a buried bit line structure inwhich the buried bit line is not in contact with the substrate or thefirst well 3 and consequently there is a higher degree of flexibilitywith regard to the terminal potentials.

In accordance with FIG. 6E2 or a third exemplary embodiment, however, itis also in turn possible for the trench insulation layer 6 to becompletely removed from the uncovered upper region of the trench in afurther, preferably wet-chemical etching process using the mask layer11, which in turn results in direct contact being made with thesubstrate or the first well 3, given suitable doping of thesemiconductor materials used.

FIG. 6F2 shows the final steps for forming the covering connecting layer12 and the highly conductive terminal layer 13, in which contextreference is made once again to the description given in connection withFIG. 5I.

FIG. 7 shows a simplified sectional view of a bit line structure inaccordance with a fourth exemplary embodiment; identical referencesymbols once again denote identical or corresponding layers inparticular to those shown in FIG. 4, and these layers will not bedescribed again below.

FIG. 7 substantially corresponds to the structure shown in FIG. 4,except that to realize the filling layer 7 and the covering connectinglayer 12, a semiconductor material which has the same conduction type asthe doping region 10 is now used. More specifically, by way of example,in situ-doped n+-polysilicon, which can already form an electricallyconductive contact with the n+-doped source region S, is used as fillinglayer 7 and covering connecting layer 12. However, since the coveringconnecting layer 12 and the substrate or the first well 3 now have adoping of the opposite conduction type, what are known as depletion orspace charge regions, which effect an insulating action in a similar wayto the trench insulation layer 6 in the second exemplary embodimentshown in FIG. 6F1, are formed at the contact surfaces between thecovering connecting layer 12 and the substrate or first well 3. In thisway, a well insulation between the buried bit line and the substrate oran associated well is obtained even when using the method steps shown inFIG. 5 and the second alternative in FIG. 6.

Furthermore, in this context it should be pointed out that the highlyconductive connecting layers 13 do not have to be formed inside thesubstrate, i.e. recessed into the doping regions 10, but rather may beformed partially or completely at the surface of the substrate in thesame way.

The disclosed embodiments have been described above on the basis of anonvolatile SNOR semiconductor memory circuit. However, it is notrestricted to this particular application and rather in the same waycomprises further semiconductor memory circuits which have acorresponding bit line structure. Furthermore, the invention is notrestricted to the silicon semiconductor substrates and materialsdescribed, but rather in the same way encompasses alternativesemiconductor materials with corresponding dopings or insulationfeatures.

LIST OF REFERENCE SYMBOLS

-   -   1, 2, 3 Substrate or corresponding wells    -   4 First auxiliary insulation layer    -   5 Hard mask layer    -   6 Trench insulation layer    -   7 Filling layer    -   8 First covering partial layer    -   9 Second covering partial layer    -   8A Covering sacrificial layer    -   10 Doping region    -   11 Mask layer    -   12 Covering connecting layer    -   13 Terminal layer    -   14 Intermediate insulation layer    -   15 Metallization layer    -   T Trench    -   SLX Buried bit line    -   DLx Surface bit line    -   BLx Bit line pair    -   WLx Word line    -   SE Switching element    -   K, DC Contact    -   STI Shallow trench isolation    -   AA Active area    -   S Source regions    -   D Drain regions

It is therefore intended that the foregoing detailed description beregarded as illustrative rather than limiting, and that it be understoodthat it is the following claims, including all equivalents, that areintended to define the spirit and scope of this invention.

1. A method for fabricating a bit line structure, comprising the stepsof: a) forming a trench (T) in a substrate (1, 2, 3); b) forming atrench insulation layer (6) at a trench surface of the trench (T); c)forming an electrically conducting filling layer (7) on the trenchinsulation layer (6) of the trench (T) in order to realize a buried bitline (SLx); d) forming a covering insulation layer (8, 9, 8A) in anupper region of the trench (T); e) forming first and second dopingregions (10) at the surface of the substrate (3); f) forming amultiplicity of covering connecting layers (12) on the filling layer(7)in partial regions of the covering insulation layer (8, 9, 8A); g)forming a multiplicity of self-aligning terminal layers (13) forelectrically connecting the multiplicity of covering connecting layers(12)to the second doping regions (10, S); h) forming an intermediateinsulation layer (14) at the surface of the substrate; i) forming anelectrically conducting layer (15) as surface bit line (DLx); and j)forming a multiplicity of contacts (DC) for electrically connecting thesurface bit line (DLx) to the first doping regions (D).
 2. The method asclaimed in patent claim 1, wherein in step a) a substrate with amultiple well structure and the trench (T) is formed into a second well(2).
 3. The method as claimed in patent claim 2, wherein in step b) athermal oxidation is formed for the purpose of forming a liner oxide astrench insulation layer (6).
 4. The method as claimed in patent claim 2,wherein in step c) a highly doped polycrystalline semiconductor materialis deposited as filler layer (7).
 5. The method as claimed in patentclaim 2, wherein in step d) the filling layer (7) is etched back in anupper region of the trench (T).
 6. The method as claimed in patent claim5, wherein in step d) a first covering partial layer (8) is formed bymeans of thermal oxidation at the surface of the filling layer (7) whichhas been etched back, and a second covering partial layer (9) forfilling the trench (T) is formed by means of a TEOS deposition process.7. The method as claimed in patent claim 2, wherein in step f) amultiplicity of partial regions of the covering insulation layer (8, 9)and of the trench insulation layer (6) are removed in the upper regionof the trench and in situ-doped semiconductor material is deposited andetched back in order to form the covering connecting layers (12).
 8. Themethod as claimed in patent claim 2, wherein in step g) the coveringconnecting layer (12) and the second doping regions (10) are etched 5back.
 9. The method as claimed in patent claim 2, wherein in step g) asilicidable material is deposited, a surface of the covering connectinglayer (12) and of the second doping regions (10) are converted using thesilicidable material, and the unconverted silicidable material isremoved again.
 10. The method as claimed in patent claim 2, wherein instep a) a Si semiconductor material is used for the substrate; and insteps c) and f) polysilicon of the opposite conduction type (p) to theconduction type (n) of the second doping regions (10) is used for theburied bit line (SLx, 7) and the covering connecting layer (12).
 11. Themethod as claimed in patent claim 1, wherein in step b) a thermaloxidation is formed for the purpose of forming a liner oxide as trenchinsulation layer (6).
 12. The method as claimed in patent claim 11,wherein in step c) a highly doped polycrystalline semiconductor materialis deposited as filler layer (7).
 13. The method as claimed in patentclaim 11, wherein in step d) the filling layer (7) is etched back in anupper region of the trench (T).
 14. The method as claimed in patentclaim 13, wherein in step d) a first covering partial layer (8) isformed by means of thermal oxidation at the surface of the filling layer(7) which has been etched back, and a second covering partial layer (9)for filling the trench (T) is formed by means of a TEOS depositionprocess.
 15. The method as claimed in patent claim 11, wherein in stepf) a multiplicity of partial regions of the covering insulation layer(8, 9) and of the trench insulation layer (6) are removed in the upperregion of the trench and in situ-doped semiconductor material isdeposited and etched back in order to form the covering connectinglayers (12).
 16. The method as claimed in patent claim 11, wherein instep g) the covering connecting layer (12) and the second doping regions(10) are etched 5 back.
 17. The method as claimed in patent claim 11,wherein in step g) a silicidable material is deposited, a surface of thecovering connecting layer (12) and of the second doping regions (10) areconverted using the silicidable material, and the unconvertedsilicidable material is removed again.
 18. The method as claimed inpatent claim 11, wherein in step a) a Si semiconductor material is usedfor the substrate; and in steps c) and f) polysilicon of the oppositeconduction type (p) to the conduction type (n) of the second dopingregions (10) is used for the buried bit line (SLx, 7) and the coveringconnecting layer (12).
 19. The method as claimed in patent claim 1,wherein in step c) a highly doped polycrystalline semiconductor materialis deposited as filler layer (7).
 20. The method as claimed in patentclaim 19, wherein in step d) the filling layer (7) is etched back in anupper region of the trench (T).
 21. The method as claimed in patentclaim 20, wherein in step d) a first covering partial layer (8) isformed by means of thermal oxidation at the surface of the filling layer(7) which has been etched back, and a second covering partial layer (9)for filling the trench (T) is formed by means of a TEOS depositionprocess.
 22. The method as claimed in patent claim 19, wherein in stepf) a multiplicity of partial regions of the covering insulation layer(8, 9) and of the trench insulation layer (6) are removed in the upperregion of the trench and in situ-doped semiconductor material isdeposited and etched back in order to form the covering connectinglayers (12).
 23. The method as claimed in patent claim 19, wherein instep g) the covering connecting layer (12) and the second doping regions(10) are etched 5 back.
 24. The method as claimed in patent claim 19,wherein in step g) a silicidable material is deposited, a surface of thecovering connecting layer (12) and of the second doping regions (10) areconverted using the silicidable material, and the unconvertedsilicidable material is removed again.
 25. The method as claimed inpatent claim 19, wherein in step a) a Si semiconductor material is usedfor the substrate; and in steps c) and f) polysilicon of the oppositeconduction type (p) to the conduction type (n) of the second dopingregions (10) is used for the buried bit line (SLx, 7) and the coveringconnecting layer (12).
 26. The method as claimed in patent claim 1,wherein in step d) the filling layer (7) is etched back in an upperregion of the trench (T).
 27. The method as claimed in patent claim 26,wherein in step d) a first covering partial layer (8) is formed by meansof thermal oxidation at the surface of the filling layer (7) which hasbeen etched back, and a second covering partial layer (9) for fillingthe trench (T) is formed by means of a TEOS deposition process.
 28. Themethod as claimed in patent claim 27, wherein in step f) a multiplicityof partial regions of the covering insulation layer (8, 9) and of thetrench insulation layer (6) are removed in the upper region of thetrench and in situ-doped semiconductor material is deposited and etchedback in order to form the covering connecting layers (12).
 29. Themethod as claimed in patent claim 27, wherein in step g) the coveringconnecting layer (12) and the second doping regions (10) are etched 5back.
 30. The method as claimed in patent claim 27, wherein in step g) asilicidable material is deposited, a surface of the covering connectinglayer (12) and of the second doping regions (10) are converted using thesilicidable material, and the unconverted silicidable material isremoved again.
 31. The method as claimed in patent claim 27, wherein instep a) a Si semiconductor material is used for the substrate; and insteps c) and f) polysilicon of the opposite conduction type (p) to theconduction type (n) of the second doping regions (10) is used for theburied bit line (SLx, 7) and the covering connecting layer (12).
 32. Themethod as claimed in patent claim 26, wherein in step f) a multiplicityof partial regions of the covering insulation layer (8, 9) and of thetrench insulation layer (6) are removed in the upper region of thetrench and in situ-doped semiconductor material is deposited and etchedback in order to form the covering connecting layers (12).
 33. Themethod as claimed in patent claim 26, wherein in step g) the coveringconnecting layer (12) and the second doping regions (10) are etched 5back.
 34. The method as claimed in patent claim 26, wherein in step g) asilicidable material is deposited, a surface of the covering connectinglayer (12) and of the second doping regions (10) are converted using thesilicidable material, and the unconverted silicidable material isremoved again.
 35. The method as claimed in patent claim 26, wherein instep a) a Si semiconductor material is used for the substrate; and insteps c) and f) polysilicon of the opposite conduction type (p) to theconduction type (n) of the second doping regions (10) is used for theburied bit line (SLx, 7) and the covering connecting layer (12).
 36. Themethod as claimed in patent claim 26, wherein in step d) a coveringsacrificial layer (8A) is formed at the surface of the trench insulationlayer (6) by means of a spacer method, and a second covering partiallayer (9) is formed by means of a TEOS deposition process in order tofill the trench.
 37. The method as claimed in patent claim 36, whereinin step f) a multiplicity of partial regions of the covering sacrificiallayer (8A) are removed in the upper region of the trench (T), and insitu-doped semiconductor material is deposited and etched back in orderto form the covering connecting layer (12).
 38. The method as claimed inpatent claim 37, wherein in step g) the covering connecting layer (12)and the second doping regions (10) are etched 5 back.
 39. The method asclaimed in patent claim 37, wherein in step g) a silicidable material isdeposited, a surface of the covering connecting layer (12) and of thesecond doping regions (10) are converted using the silicidable material,and the unconverted silicidable material is removed again.
 40. Themethod as claimed in patent claim 37, wherein in step a) a Sisemiconductor material is used for the substrate; and in steps c) and f)polysilicon of the opposite conduction type (p) to the conduction type(n) of the second doping regions (10) is used for the buried bit line(SLx, 7) and the covering connecting layer (12).
 41. The method asclaimed in patent claim 36, wherein in step f) a multiplicity of partialregions of the covering sacrificial layer (8A) of the trench insulationlayer (6) and of the second covering partial layer (9) are removed inthe upper region of the trench (T), and in situ-doped semiconductormaterial is deposited and etched back in order to form the coveringconnecting layer (12).
 42. The method as claimed in patent claim 41,wherein in step g) the covering connecting layer (12) and the seconddoping regions (10) are etched 5 back.
 43. The method as claimed inpatent claim 41 wherein in step g) a silicidable material is deposited,a surface of the covering connecting layer (12) and of the second dopingregions (10) are converted using the silicidable material, and theunconverted silicidable material is removed again.
 44. The method asclaimed in patent claim 41, wherein in step a) a Si semiconductormaterial is used for the substrate; and in steps c) and f) polysiliconof the opposite conduction type (p) to the conduction type (n) of thesecond doping regions (10) is used for the buried bit line (SLx, 7) andthe covering connecting layer (12).
 45. The method as claimed in patentclaim 36, wherein in step g) the covering connecting layer (12) and thesecond doping regions (10) are etched 5 back.
 46. The method as claimedin patent claim 36, wherein in step g) a silicidable material isdeposited, a surface of the covering connecting layer (12) and of thesecond doping regions (10) are converted using the silicidable material,and the unconverted silicidable material is removed again.
 47. Themethod as claimed in patent claim 36, wherein in step a) a Sisemiconductor material is used for the substrate; and in steps c) and f)polysilicon of the opposite conduction type (p) to the conduction type(n) of the second doping regions (10) is used for the buried bit line(SLx, 7) and the covering connecting layer (12).
 48. The method asclaimed in patent claim 1, wherein in step f) a multiplicity of partialregions of the covering insulation layer (8, 9) and of the trenchinsulation layer (6) are removed in the upper region of the trench andin situ-doped semiconductor material is deposited and etched back inorder to form the covering connecting layers (12).
 49. The method asclaimed in patent claim 48, wherein in step g) the covering connectinglayer (12) and the second doping regions (10) are etched 5 back.
 50. Themethod as claimed in patent claim 48, wherein in step g) a silicidablematerial is deposited, a surface of the covering connecting layer (12)and of the second doping regions (10) are converted using thesilicidable material, and the unconverted silicidable material isremoved again.
 51. The method as claimed in patent claim 48, wherein instep a) a Si semiconductor material is used for the substrate; and insteps c) and f) polysilicon of the opposite conduction type (p) to theconduction type (n) of the second doping regions (10) is used for theburied bit line (SLx, 7) and the covering connecting layer (12).
 52. Themethod as claimed in patent claim 1, wherein in step g) the coveringconnecting layer (12) and the second doping regions (10) are etched 5back.
 53. The method as claimed in patent claim 52, wherein in step g) asilicidable material is deposited, a surface of the covering connectinglayer (12) and of the second doping regions (10) are converted using thesilicidable material, and the unconverted silicidable material isremoved again.
 54. The method as claimed in patent claim 52, wherein instep a) a Si semiconductor material is used for the substrate; and insteps c) and f) polysilicon of the opposite conduction type (p) to theconduction type (n) of the second doping regions (10) is used for theburied bit line (SLx, 7) and the covering connecting layer (12).
 55. Themethod as claimed in patent claim 1, wherein in step g) a silicidablematerial is deposited, a surface of the covering connecting layer (12)and of the second doping regions (10) are converted using thesilicidable material, and the unconverted silicidable material isremoved again.
 56. The method as claimed in patent claim 55, wherein instep a) a Si semiconductor material is used for the substrate; and insteps c) and f) polysilicon of the opposite conduction type (p) to theconduction type (n) of the second doping regions (10) is used for theburied bit line (SLx, 7) and the covering connecting layer (12).
 57. Themethod as claimed in patent claim 1, wherein in step a) a Sisemiconductor material is used for the substrate; and in steps c) and f)polysilicon of the opposite conduction type (p) to the conduction type(n) of the second doping regions (10) is used for the buried bit line(SLx, 7) and the covering connecting layer (12).